The definition of high performance time-critical systems implies the design of highly integrated electronic devices that run sophisticated software. This trend leads to a sharp increase in complexity in embedded systems. Extensive analysis of the hardware/software architectures of embedded systems with respect to their timing behavior under realistic working scenarios is necessary to avoid costly design cycles. The analysis of the timing behavior of software running in parallel on complex multi-core platforms is difficult.

In the field of time response analysis of multi-core systems, simulation-based approaches and mathematical formal methods exist. Both approaches struggle with scaling problems. Our work aims to increase the scalability of the analysis methods by using probability-based simulation techniques.

Our goal in this project is to demonstrate potential improvements in the analyzability of architectures with respect to size (more cores) and complexity (heterogeneity and memory hierarchies) by using probability-based methods instead of existing analytical or state-based formal approaches.