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All authors

Schwarz, A. and Mertsching, B. and Brucke, M. and Kollmeier, B. and Tschorz, J. and Nebel, W.

Abstract

A digital VLSI implementation of an algorithm model-ing the effective signal processing of the human auditory system is presented. The model consists of several stages psychoacoustically and physiologically motivated by the signal processing in the human ear and was successfully applied to various speech processing applications. The pro-cessing scheme was partitioned for implementation in a set of three chips. Due to local properties of the signal dynamic and the necessary arithmetical precision different ap-proaches for number representation and appropriate arith-metic operators were investigated and implemented. It is demonstrated how an application of the model has been used to determine the necessary wordlengths for a transfer of the algorithm into a version suitable for hardware imple-mentation. Fix point arithmetic is used in the linear parts of the origin algorithm and a special small floating point op-erator set was developed for the nonlinear part. This part was coded in behavioral VHDL and synthesized with Synopsys Behavioral Compiler. The hardware algorithm is being evaluated on different implementation levels for a FPGA and will be manufactured as ASICs in a later ver-sion. The presented FPGA chip set will be combined with a commercial DSP system (TMS320C6201) for real time and reconfigurable signal processing.

Publishing date

01 / 1999

Type of Publication

inproceedings

Organization

Proceedings of the 25th EOROMICRO Conference, Milano, Italy