Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems - OFFIS

Your browser does not support JavaScript!

To use all the features of this page, you need JavaScript!<br> Please update your browser or enable JavaScript in your settings.

Home
OFFIS
Publikationen
Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems

Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems

Export

All authors

Helms, Domenik and Nebel, Wolfgang

Booktitle

Proceedings on the 14th IEEE Internactional Conference on Electronics, Circuits, and Systems

Publishing date

12 / 2007

Type of Publication

inproceedings

Projects

CLEAN
Controlling LEAkage power in NanoCMOS SoCs

OFFIS Autoren

Wolfgang Nebel

Privacy Data Transparency Contact Legals