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Radetzki, Martin and Putzke-Röming, Wolfram and Nebel, Wolfgang

Abstract

Objective VHDL, an object-oriented extension to VHDL, has been designed within the OMI-ESPRIT project REQUEST to facilitate hardware modeling at a higher level of abstraction and with increased potential for reuse. In this paper, we present a preprocessor tool set for the translation of Objective VHDL into VHDL, allowing to use the new language with existing simulation and synthesis environments. Since the back end processing (simulation, synthesis) takes place on VHDL level, the correlation of the generated VHDL to the original Objective VHDL sources should be understood by the user and will therefore be outlined. The presentation is based on the example of object-oriented buffer (FIFO, LIFO) data types that can be synthesized into gates.

Publishing date

01 / 1998

Type of Publication

inproceedings

Organization

FDL 1998, Forum on Design Languages, Lausanne / Schweiz