In only 5 years, leakage developed from an academic corner phenomenon to a central problem of embedded system design. In sub 90nm designs the leakage power is already exceeding the dynamic power. The intention of this tutorial is to review the mechanisms causing leakage and the parameters and imperfections causing leakage variation. Afterwards, the state-of-the-art in leakage reduction and management methodologies is presented with a focus on transistor design, leakage management, and low leakage SRAM architectures.