Motivation:

This proposal is meant to contribute to the efficient design of dynamically reconfigurable FPGAs. A design method will be developed and its efficiency will be proved by a prototype, which for the first time uses methods of object oriented programming for specification and modeling of the dynamic aspects of partial reconfigurable hardware. Partial dynamically reconfigurable FPGAs allow more efficient usage of limited hardware resources by time-shifted usage of identical resources for different purposes in a time sharing like approach compared to the exclusive use of hardware resources for each task.

 

The concept of polymorphism known from the object oriented programming approach has simularities to this in the dynamic behavior of objects. Objects change their properties during runtime. A contemporaneous availability of all characteristics of a hardware unit is necessary for a static hardware but unsatisfactory under the aspect of efficiency of hardware usage. Partial dynamic reconfigurable FPGAs allow for providing only the current configuration in principle.

 

For the first time there is a object oriented hardware design language available developed by the maker of this proposal which is synthesizable to hardware and has support for polymorphic constructs. The goal of this proposal is to apply these abilities to reconfigurable hardware in an efficient way.

 

Project goals:

In the first period of funding a concept for simulation of dynamic object behavior on dynamic reconfigurable hardware is to be developed. The existing simulation technique which is based on SystemC is to be extended by appropriate concepts for modeling reconfiguration. Especially timing behavior checks of the intended implementation (profiling) shall be made possible.

 

Further concepts for the existing synthesis tool for SystemC-Plus shall be developed which allow a mapping of descriptions for polymorphic objects on synthesizable SystemC descriptions. A concept for a reconfiguration controller is to be developed, which performs the partial reconfiguration step during runtime.

 

In later periods of funding these concepts are to be refined and implemented in a prototype. Futher a cooperation with the workgroup of Prof. Ramming is planned for investigation in methods for architecture synthesis and optimization of dynamic reconfigurable FPGAs.