MoRV Modelling reliability under variability
Motivation
While feature sizes are continuously scaled towards atomic dimensions, industry is increasingly confronted with unexpected physical artefacts to be considered at each new technology node. Among these, process variation and parameter degradation lead to reliability concerns impacting integrated circuit design at all abstraction levels. As variation and degradation may become a limiting factor for future scaled technologies, there has been a tremendous research effort in understanding these artefacts. Versatile tools, allowing consideration of these artefacts and their combined impact during the design of ICs are still in their infancy.
Rather than developing yet another design support methodology, we aim to combine and refine existing reliability and variability prediction methodologies at the abstraction layers with highest industrial importance: Register transfer (RT) level - usual design entry, gate level – where most design for reliability (DfR) techniques are applied, and transistor level - where final sign-off is made.
MoRV will cover the strong relationship between variability and ageing, which are usually treated separately, fostering the idea of treating ageing as a form of time-dependent variability. Combined models from transistor, over gate, to RT level will be characterized directly from silicon measurement and all models will be able to interpret the same characterization data base from the silicon measurement.
Funding:
MoRV is funded in the 7th Framework ICT of the European Union (Projectnumber 619234).
External Leader
Dr. Domenik HelmsScientific Director
Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel, Kay-Uwe Giering, Roland Jancke, Gerhard Rzepa, Tibor Grasser, Markus Karner, Praveen Raghavan, Ben Kaczer, Dan Alexandrescu, Adrian Evans, Gunnar Rott, Peter Rotter, Hans Reisinger, Wolfgang Gustin; SELSE 12 proceedings; 03 / 2016
Enrico Costenaro, Domenik Helms, Nematollah Bidokhti, Adrian Evans, Maximilian Glorieux and Dan Alexandrescu; DAC - Design Automation Conference; 06 / 2015
Eilers, Reef and Metzdorf, Malte and Helms, Domenik and Nebel, Wolfgang; Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED); 2014
Malte Metzdorf, Domenik Helms, Reef Eilers, Wolfgang Nebel; DATE - Design, Automation, and Test in Europe; 03 / 2015
Nils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel; DATE; 03 / 2016
Ahmet Unutulmaz, Domenik Helms, Reef Eilers, Malte Metzdorf, Ben Kaczer, Wolfgang Nebel; DATE; 03 / 2016
Domenik Helms ; Reef Eilers ; Malte Metzdorf ; Wolfgang Nebel; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; 11 / 2017
HW. Karner, C. Kernstock, Z. Stanojevi´c, O. Baumgartner, F. Schanovsky, M. Karner, D. Helms, R. Eilers, M. Metzdorf; Proceedings of the 2017 Intl. Symp. on VLSI Technology, Systems and Application; 04 / 2017
Nils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel; Proceedings of the 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS); 09 / 2017
Sunil Malipatlolla, Ahmet Unutulmaz, Domenik Helms, Wolfgang Nebel; Proceedings of the 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS); 09 / 2017
Domenik Helms, Daniele Rossi, Haider Muhi Abbas, Mohd Syafiq Mispan, Shengyu Duan, Lorena Anghel, Helena-Maria Dounavi, Gaole Sai; 2020
Domenik Helms, Reef Eilers, Malte Metzdorf, Wolfgang Nebel; IEEE Trans. on Computer-Aided Design of ICs and Systems; 0August / 2018
Domenik Helms, Reef Eilers, Malte Metzdorf, Wolfgang Nebel; 0March / 2015
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