Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking
Fakih, Maher and Grüttner, Kim and Fränzle, Martin and Rettberg, Achim
Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2013
The timing predictability of embedded systems withhard real-time requirements is fundamental for guaranteeingtheir safe usage. With the emergence of multicore platformsthis task became very challenging. In this paper, a model-checking based approach will be described which allows us toguarantee timing bounds of multiple Synchronous Data FlowGraphs (SDFG) running on shared-bus multicore architectures.Our approach utilizes Timed Automata (TA) as a commonsemantic model to represent software components (SDF actors)and hardware components of the multicore platform. These TAare explored using the UPPAAL model-checker for providing thetiming guarantees. Our approach shows a significant precisionimprovement compared with the worst-case bounds estimatedbased on maximal delay for every bus access. Furthermore,scalability is examined to demonstrate analysis feasibility forsmall parallel systems.
03 / 2013
inproceedings
European Design and Automation Association
DATE '13
MotorBrain
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Nanoelectronics for Electric Vehicle Intelligent Failsafe PowerTrain
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