MotorBrain Nanoelectronics for Electric Vehicle Intelligent Failsafe PowerTrain

Ziele

The intention of the MotorBrain project is to develop sustainable drive train technologies and control concepts/ platforms for inherently safe and highly efficient Electric Vehicle (EV) powertrains of the 3rd Generation. The envisaged EV-Powertrain will enable significant steps ahead in terms of:

  • Overall energy efficiency: The next generation EV-Powertrains shall improve energy efficiency by 20%.
  • Development of novel smart and intrinsic failsafe electrical powertrain concepts: Powertrain concepts will not only focus on new highly efficient smart motor management systems and torque-dense motor concepts, furthermore intelligent integration concepts for passive components, power converters as well as new concepts for modular storage systems will be derived and verified. By exploding the benefits of higher integrated subsystems of the EV-powertrain it is expected to further enhance the efficiency and reliability of EV-Powertrains without impeding production costs. Moreover is it envisaged to strengthen the sustainability by improving recyclability and alleviating the dependency on rare-earth magnets.
  • Deriving new EV architectures, sensors and microcontroller concepts/ platforms: Core aim of the MotorBrain Project is to strengthen the EV related industries by achieving technological leading positions through the development of intrinsic fail-safe powertrains and energy management systems in order to enhance the overall reliability, safety and efficiency of EVs. In particular the safety of the next Generation EV will be improved using; redundancy concepts at different subsystem levels, sensors in combination with advanced control mechanisms as well as multi-core ECU’s. Intelligence will be enhanced through embedded software in a highly distributed control system, taking into account the interaction between hardware and software within the physical environment.

 

The project addresses the highly challenging research on power and high voltage electronic systems beyond state of the art. Smart miniaturized systems including subsystems, system-layers and vehicle demonstrators will be derived and via the interaction of all systems they comprise the full supply chain of electric drives for EVs.

Personen

Wissenschaftliche Leitung

Publikationen
Virtual-Platform in the Loop Simulation for Accurate Timing Analysis of Embedded Software on Multicore Platforms

Fakih, Maher and Grüttner, Kim; ASIM-Treffen der Fachgruppen "Simulation technischer Systeme" und "Grundlagen und Methoden in Modellbildung und Simulation; 02 / 2012

Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking

Fakih, Maher and Grüttner, Kim and Fränzle, Martin and Rettberg, Achim; Proceedings of the Conference on Design, Automation and Test in Europe (DATE) 2013; 003 / 2013

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

Fakih, Maher and Grüttner, Kim and Fränzle, Martin and Rettberg, Achim; Embedded Systems: Design, Analysis and Verification; 006 / 2013

Hardware-Based Real-Time Simulation on the Raspberry Pi

Jörg Walter, Maher Fakih and Kim Grüttner; 2nd Workshop on High-performance and Real-time Embedded Systems (HiRES 2014); 001 / 2014

Multicore Performance analysis of a Multi-phase Electrical Motor Controller

Fakih, Maher and Grüttner, Kim and Fränzle, Martin and Rettberg, Achim; Proceedings of the Embedded Real Time Software and Systems Congress (ERTS²) 2014; 02 / 2014

State-Based Real-Time Analysis of SDF Applications on MPSoCs with Shared Communication Resources

Maher Fakih and Kim Grüttner and Martin Fränzle and Achim Rettberg; Journal of Systems Architecture (JSA): the EUROMICRO Journal; 0oct / 2015

MotorBrain: Model-Based Design and Virtual Integration of an Intelligent and Safe Electrical Powertrain

Sven Rosinger, Maher Fakih and Jörg Walter; University Booth at DATE 2014; 003 / 2014

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

Maher Fakih, Kim Grüttner, Martin Fränzle, and Achim Rettberg; International Embedded Systems Symposium (IESS); 06 / 2013

State-Based Real-Time Analysis of SDF Applications on Multi-Cores

Maher Fakih and Kim Grüttner and Martin Fränzle and Achim Rettberg; 1st International Workshop on Investigating Dataflow in Embedded computing Architecture (IDEA); 01 / 2015

Partner
STMicroelectronics srl
www.st.com
GREENPOWERtech
www.greenpower.es
EGSTON System Electronics Eggenburg GmbH
www.egston.com
All Green Vehicles
NXP Semiconductors Hamburg
www.nxp.com
The University of Sheffield
www.shef.ac.uk
QinetiQ Ltd.
www.qinetiq.com
Höganäs AB
www.hoganas.com
Universidad de Sevilla
www.us.es
IMT Bucharest - National Institute for Research and Development in Microtechnologies
www.imt.ro
Istituto P.M. s.r.l.
ROBOX S.P.A.
www.robox.it
Arcotronics
www.arcotronics.com
Politecnico di Torino
www.polito.it
Infineon Technologies AG
www.infineon.com
CRF - Centro Ricerche Fiat S.C.p.A.
www.crf.it
Institut mikroelektronických aplikací s.r.o.
www.ima.cz
VYSOKÉ UČENÍ TECHNICKÉ V BRNĚ
www.vutbr.cz
ZF Friedrichshafen AG
www.zf.com
AVL LIST GmbH
www.avl.com
FH Joanneum GmbH
www.fh-joanneum.at
AIT Austrian Institute of Technology
www.ait.ac.at
Robert Seuffer GmbH & Co. KG
www.seuffer.de
TU Dresden
tu-dresden.de
Hochschule Amberg-Weiden
www.haw-aw.de
E3/DC GmbH
www.e3dc.com
Volkswagen AG
www.volkswagen.de

Laufzeit

Start: 01.07.2011
Ende: 30.06.2014

Website des Projekts